Voltage Scaling and Limits to Energy Efficiency for CMOS-based SCRL

This is a working memo, not yet finished, which analyzes how the minimum energy per operation achievable with SCRL, an adiabatic circuit technique, scales with speed, threshold voltage, and temperature, and how its energy efficiency compares to that achievable using standard CMOS.

Anyway, here is what I've written up so far.

This paper is part of the M series of working memos produced by the MIT Reversible Computing Project.


Michael Frank
Last modified: Mon Jan 6 18:15:29 EST