For an example 0.5 µm technology and a densely packed design that minimizes price/performance, we estimate the optimal voltage would be about 0.7 V, given a maximum heat flux of 100 W/cm2. At this voltage, the RC delay and dissipation time are both around 43 ps, suggesting a multi-gigaHertz maximum clock speed which is 20 times faster than the speed limit due to power dissipation when running at the 3.3 V voltage level for which the technology was designed. Furthermore, as device lengths decrease, the optimal voltage scales down proportionately, and the speed when running at this voltage increases proportionately as well.
However, below about 0.05 µm length scales, we will be unable to lower the power dissipation of room-temperture devices enough to continue these speed improvements, since sub-threshold conduction will then dominate the power consumption, and prevent further increases in device density. Soon after this point, speeds will be limited to a constant, determined by the power dissipation per device, regardless of any further decreases in line widths. Any improvements in price/performance beyond this point will require either sophisticated cooling systems, low-temperature operation, or some new, non-MOSFET device technology.