Key: ---- r,rsd,rd,rs,ra,rb = 5-bit register identifier. No-Op if rd is the same reg as rs or rt. imm = 16 bit signed immediate [imm] imm sign extended to 32 bits off = 16 bit signed offset loff = 26 bit signed offset dir = +1/-1 bit where +1=forward or -1=reverse Mnem. Args. Forwards behavior ------ --------- ------------------ ADD rsd,rt rsd += rt ADDI rsd,imm rsd += [imm] ANDX rd,rs,rt rd ^= rs&rt ANDIX rd,rs,imm rd ^= rs&[imm] BEQ ra,rb,off if ra=rb, BR+=off BGEZ rb,off if rb>=0, BR+=off BGTZ rb,off if rb>0, BR+=off BLEZ rb,off if rb<=0, BR+=off BLTZ rb,off if rb<0, BR+=off BNE ra,rb,off if ra!=rb, BR+=off BRA loff BR+=loff EMIT r 0 -> r -> bitsink (irrev.) EXCH rd,ra rd <-> mem[ra] NORX rd,rs,rt rd ^= ~(rs|rt) NEG rsd rsd = -rsd ORX rd,rs,rt rd ^= rs|rt ORIX rd,rs,imm rd ^= rs|[imm] RBRA loff BR-=loff, dir=reverse RL rsd,imm rsd = rsd rol imm RLV rsd,rt rsd = rsd rol rt RR rsd,imm rsd = rsd ror imm RRV rsd,rt rsd = rsd ror rt SEE r r ^= next word fr. input stream SHOW r echo r to output stream SLLX rd,rs,imm rd ^= rs<<imm SLLVX rd,rs,rt rd ^= rs<<rt SLTX rd,rs,rt rd ^= (rs<rt)?1:0 SLTIX rd,rs,imm rd ^= (rs<imm)?1:0 SRAX rd,rs,imm rd ^= rs>>imm SRAVX rd,rs,rt rd ^= rs>>rt SRLX rd,rs,imm rd ^= (unsigned)rs>>imm SRLVX rd,rs,rt rd ^= (unsigned)rs>>rt SUB rsd,rt rsd -= rt SWAPBR r r<->BR XOR rsd,rt rsd ^= rt XORI rsd,imm rsd ^= [imm] PC update between instructions: if (BR=0) pc+=dir else pc+=BR*dir