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MIT REVERSIBLE COMPUTING PROJECT MEMO #M7 Modifications to PISA architecture to support guaranteed reversibility and other features WORKING DRAFT MEMO Revision: 1.3

Michael P. Frank
http://www.ai.mit.edu/mpf

MIT AI Lab
545 Technology Sq.
Cambridge, MA 02139

Started February 28, 1997.
RevisionDate: 1997/06/30 20:52:38
Typeset Wed Jul 23 13:48:32 EDT 1997 .
A current version is available online at
http://www.ai.mit.edu/mpf/rc/memos/M07/M07_revarch.html

Abstract:

This document specifies a number of proposed modifications to the PISA (Pendulum Instruction Set Architecture) assembly-level instruction set and instruction semantics, the original version of which was specified in http://www.ai.mit.edu/ cvieri/pisa.ps, version of May 5. The advantages of these new modifications are:
Machine operation may be guaranteed reversible independently of the correctness of user source programs, while still allowing programs to compile to efficient code.
The number of different instruction opcodes is reduced.
Subroutine calls require fewer instructions in the caller.
The direction of program execution can be controlled in software, allowing a single copy of a subroutine to be called either forwards or in reverse.
Instruction and data memories are merged, making program loaders and other OS features newly possible.
I/O instructions are provided.
A special instruction for hardware garbage disposal is provided.
We do not modify the overall instruction set encoding in terms of the number, size, or meaning of the various bit-fields. However, some opcodes will need to be reassigned since some instructions have been added, and others removed. This document does not specify the new opcodes.

Michael Frank
Wed Jul 23 13:48:27 EDT 1997