The AdiaMEMS Project                     

 

This SRC-funded research project (part of the RevComp project at UF) has the goal of investigating whether reversible computing techniques can be made practical for near-term, ultra-low-power digital applications, by using a simple 2-level, truly-adiabatic CMOS logic style called 2LAL (developed at UF in Spring of 2000), implemented in TSMC 0.18 micron technology, and driven by high-Q custom MEMS oscillators fabricated on the same chip via a custom post-CMOS DRIE process developed at UF.  We have already designed and received prototype resonator parts which we are post-etching into a TSMC 0.35 micron die and testing.  We have also performed simulations in Cadence to accurately determine the power versus frequency curve potentially achievable in our adiabatic circuits compared with conventional voltage scaling in the same process technology, when both techniques are voltage-optimized for minimum power dissipation at a given frequency.  Preliminary simulation results obtained so far suggest that we might obtain at least an order of magnitude higher operating frequency than voltage scaling, in the context of an ultra-low application power constraint on the order of a few picowatts per logic gate.  We have received approval from MOSIS to fabricate a test chip to verify our predictions.  –mpf 6/28/04

Project Members

  • PI: Michael P. Frank (CISE/ECE Depts.), mpf@cise.ufl.edu.
  • Co-PI: Huikai Xie (ECE Dept.), hkxie@ece.ufl.edu.
  • Informal collaborators:  Bill Eisenstadt, Khai Ngo, Toshi Nishida (ECE Dept.)
  • Students: Krishna Natarajan, Venkiteswaran Anantharam, Maojiao He, Umamaheswari Aghoram  (ECE Dept.)
  • Program manager:  Lalita Manchanda (SRC, Cross-Disciplinary Semiconductor Research Program)

Funding Proposals

The original white paper proposal to the SRC CSR program, which kicked off the project:

 

 

This proposal to MOSIS for a process donation is intended to fund fabrication of a prototype integrated MEMS/CMOS die.

 

  • Huikai Xie, Michael Frank, “A fully-adiabatic logic test chip based on the 4-phase 2LAL (2-Level Adiabatic Logic) family, with integrated MEMS postprocessing for high-quality energy recovery,” draft proposal to MOSIS, as of May 9, 2004.  Approved May 21.  Draft PDF at http://revcomp.info/legacy/revcomp/AdiaMEMS/MOSIS-proposal-draft.pdf.

Posters

This poster was prepared by the AdiaMEMS project’s students and presented at the ECE department’s External Research Day, April 2004.

 

Papers

This paper, presented at MLPD ’04 in June, describes our initial resonator designs.

 

  • Venkiteswaran Anantharam, Maojiao He, Krishna Natarajan, Huikai Xie, Michael P. Frank, “Driving Fully-Adiabatic Logic Circuits Using Custom High-Q MEMS Resonators,” presented at the 2004 workshop on Methodologies for Low Power Design, part of the ESA ’04 (Embedded Systems and Applications) conference, held in Las Vegas, Nevada, June 21-24, 2004.  Paper in PDF format at http://revcomp.info/legacy/revcomp/AdiaMEMS/MLPD-04.pdf.  Published in Proceedings of the International Conference on Embedded Systems & Applications, ESA ’04, H.R. Arabnia, M. Guo, & L. T. Yang, eds., CSREA Press, pp. 5-11.  Talk slides in PDF format at http://revcomp.info/legacy/revcomp/AdiaMEMS/MLPD04-Talk.pdf.

Invited Talks

  • Michael P. Frank (with some slides contributed by Huikai Xie and Maojiao He), “Reversible Supercomputing: Beyond the Limits of Moore’s Law,” invited talk given at Sandia National Labs, May 12, 2004.  Host: Erik DeBenedictis.  Talk slides and notes in PDF format at http://revcomp.info/legacy/revcomp/AdiaMEMS/Sandia-talk.pdf.
  • Michael P. Frank (with slides by Xie and He), “Adiabatic, Reversible Computing for Ultra-Power-Efficient DSP,” invited talk given at Texas Instruments, June 4, 2004.  Host: Dr. Dennis D. Buss, VP of Silicon Technology Development.  Talk slides in PDF (2 per page) format at http://revcomp.info/legacy/revcomp/AdiaMEMS/TI-talk-2004.pdf.

Patents

This provisional patent application (no number assigned yet) was submitted by UF to the U.S. Patent Office on May 12, 2004.

 

Selected Results

The below chart plots our actual circuit simulation results from Cadence for the TSMC 0.18µm technology, showing that our 2LAL adiabatic logic style can potentially achieve up to 100× higher operating frequencies than standard CMOS when both technologies are restricted to an ultra-low power level of 1 pW per nFET (1.5 MHz vs. 10 kHz), and it can potentially achieve 300× lower power consumption per device than standard CMOS when both technologies are run at the same frequency of 1 MHz (0.35 pW vs. 250 pW).  Some important caveats are noted.

The below chart shows that good results compared to standard CMOS can still be obtained even for a more complex structure such as a 32-bit adder.  Our Cadence simulations verify that our adiabatic adder can operate 20x faster (400 kHz vs. 20 kHz) than a 0.5V standard CMOS adder when there is a constraint that neither adder is allowed to dissipate more than 3 nW of power in a unit having a throughput of 1 add per cycle.  (I.e., 1 billion of our adders running in parallel would dissipate as little as 3 watts of power, while performing 400 trillion 32-bit adds per second!)

Long-Term Prospects

We feel that perhaps the best prospect for reversible computing technologies to be able to penetrate into the broader computing market (beyond niche ultra-low-power apps) involves the development of novel reversible device technologies which would allow us to lower power dissipation dramatically while remaining at the high frequencies desired for good serial (thread) performance (e.g. 1 GHz and higher).  Fortunately, there is potentially a lot of room for further improvement of reversible devices, in contrast to the relatively nearby limits that irreversible technology faces.  The below chart illustrates how much various proposed reversible device technologies might further improve power-performance at desirable frequencies.

Page last modified no earlier than 5/19/04.